The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices having a gate electrode and methods of fabricating the same.
As semiconductor devices become more highly integrated, a channel length (e.g., a width of a gate electrode) of a metal-oxide-semiconductor (MOS) transistor therein has generally been reduced. The reduction of the channel length may lead to an increase of electrical resistance of the gate electrode. A multi-layered conductive film has been widely used as the material of the gate electrode to reduce the electrical resistance thereof. For example, the gate electrode may be formed of a combination layer, such as a polycide layer that includes a polysilicon layer and a metal silicide layer having a low resistivity. However, when the gate electrode is formed as a polycide layer, the polycide layer may exhibit a non uniform interface profile between the polysilicon layer and the metal silicide layer in a subsequent annealing process.
In general, the gate electrode is formed by patterning the polycide layer using a photolithography process and an etch process, and a re-oxidation annealing process is performed to cure etch damage caused to a gate insulating layer under the gate electrode during the etch process for forming the gate electrode. However, the gate electrode may lean during the re-oxidation annealing process. The gate leaning phenomenon may be illustrated using an oxidation enhanced silicon consumption model. The oxidation enhanced silicon consumption model may include two components, e.g., a silicon consumption component and a silicon pumping component.
The silicon consumption component relates to a phenomenon that silicon atoms in the polysilicon layer are consumed at an interface between the polysilicon layer and the metal silicide layer during the re-oxidation annealing process. The silicon consumption may occur when the metal silicide layer is a metal rich silicide layer. The silicon pumping component relates to a phenomenon that silicon atoms in the polysilicon layer are moved to form an oxide layer of the metal silicide layer during the re-oxidation process. In other words, when the metal silicide layer is oxidized, metal atoms and silicon atoms in the metal silicide layer are not consumed. Also, the silicon atoms in the polysilicon layer are generally moved by grain boundary diffusion during the re-oxidation process.
When the gate leaning phenomenon occurs, two adjacent gate electrodes may be electrically connected and voids may be generated in an interlayer insulating layer that is formed on the gate electrodes. This gate leaning phenomenon may be more severe when fabricating a MOS transistor having a recessed channel (e.g., a recessed gate). The MOS transistor having a recessed channel has been proposed to suppress a short channel effect of the MOS transistor without any area penalty. The recessed channel may be formed by etching a portion of an active region, and a gate electrode may be formed by stacking a polysilicon layer filling the recessed channel and a metal silicide layer on the polysilicon layer. In this case, a profile of the recessed channel may be transferred to an interface between the polysilicon layer and the metal silicide layer. Thus, the gate leaning phenomenon may more readily occur during fabrication of the MOS transistor having the recessed channel.